About The Role and Team Quantum Motion is a fast-growing quantum computing scale-up based in London founded by internationally renowned researchers from UCL and Oxford University with over 40 years’ experience in developing qubits and quantum computing architectures. Bringing together state-of-the-art cryogenic facilities and an outstanding interdisciplinary team, we are developing quantum processors based on industrial-grade silicon chips, with the potential to radically transform computing power in areas such as materials modelling, medicine, artificial intelligence and more. Our Team Since 2021 our team has been listed every year in the “Top 100 Startups worth watching” in the EE Times in 2021 and 2022, and our technology breakthroughs have been featured in The Telegraph, BBC and the New Statesman. Our founders are internationally renowned researchers from UCL and Oxford University who have pioneered the development of qubits and quantum computing architectures. Our chairman is the co-founder of Cadence and Synopsys, the two leading companies in the area of Electronic Design Automation. We’re backed by a team of top-tier investors, and we have recently closed our Series C funding of $160 million. We bring together the brightest quantum engineers, integrated circuit (IC) engineers, quantum computing theoreticians and software engineers to create a unique, world-leading team, working together closely to maximise our combined expertise. Our collaborative and interdisciplinary culture is an ideal fit for anyone who thrives in a cutting-edge research and development environment focused on tackling big challenges and contributing to the development of scalable quantum computers based on silicon technology. This is a rare and exciting opportunity to be an employee at a scale-up shaping the future of quantum computing. There are vast opportunities for professional growth and to make an impact within the company. Our team of 100+ is based across London, Oxford, San Sebastián and Sydney, with our primary hub in Islington (London). Functions of the Role This senior position operates at the critical intersection of sub-Kelvin sub-system electronics and quantum processor architectures, directly addressing the interconnect bottleneck in scalable quantum computing systems. The role spans the full digital IC design cycle—including initial microarchitecture specification, RTL development, Verilog-AMS co-simulation, physical implementation (PnR/CTS), low-power synthesis, static timing analysis (STA), and full tape-out signoff. The ultimate objective is the realization of ultra-low-power, high-density cryogenic control ICs tailored for fault-tolerant quantum computing scale-out. • Position Title:  Senior Digital Designer (Front-End & Back-End) • Domain Focus:  Ultra-Low-Power Cryogenic CMOS (Cryo-CMOS) Digital Control Sub-circuits • Design Scope:  Full Lifecycle (RTL Development, AMS Co-Simulation, Physical Implementation, Low-Power Synthesis, and Tape-Out Signoff) • Core Chip Architecture Target: Cryogenic digital logic blocks operating at sub-Kelvin regimes ( Experience - Essentials • Education: Master's degree or Ph.D. in Electrical Engineering, Microelectronics, Computer Engineering, or related technical discipline. • Chip Design Experience: 5+ years of hands-on digital and mixed-signal IC design, demonstrating successful completion of at least 2 tape-outs on advanced semiconductor nodes  • Hardware Coding: Proficiency in Verilog and SystemVerilog for synthesizable RTL development and Verilog-AMS/SystemVerilog-Real-Math for mixed-signal co-simulation and testbench environments. • Design Tools: Proven proficiency with industry-standard EDA toolchains (e.g., Cadence Virtuoso/Innovus/Xcelium, Synopsys Design Compiler) for mixed-signal simulation, synthesis, and verification. • Physical Layout: Demonstrated capability in transforming RTL into GDSII/OASIS physical layouts, floorplanning, power grid synthesis, clock tree synthesis (CTS), multi-corner multi-mode static timing analysis (MCMM STA), and physical signoff (DRC/LVS/ERC). • Communication & Logic Design: Experience architecting high-speed serial interconnect protocols (e.g., custom SPI, AXI, SerDes) and complex finite-state machine (FSM) control logic. • Low Power & Thermal Management: Deep expertise in low-power dissipation techniques (clock gating, power gating, dynamic voltage scaling) within stringent thermal lift budgets of cryogenic cooling systems. Experience - Desirable • Cryogenic CMOS Experience: Hands-on experience designing, modeling, or characterizing CMOS circuits at sub-4.2 K temperatures and understanding cryo-specific transistor behavior. • Mixed-Signal & AMS Interfaces: Direct integration of digital logic with precision analog/RF front-ends (ADCs, DACs, LNAs, AWGs) for qubit control and readout. • Quantum Architecture Awareness: Familiarity with quantum control interfaces, pulse generation, error correction, or cryogenic spin qubit electronics • Low-Power Verification & UPF/CPF: Proficiency in power-aware simulation using IEEE 1801 UPF/CPF, formal LEC, and power signoff tools (Voltus, PrimePower). • Advanced Process Nodes: Experience with sub-28nm nodes, with a strong preference for FD-SOI or FinFET technologies. • EDA Scripting & Automation: Strong scripting skills (TCL, Python) to automate synthesis, physical design, and verification flows. • DFT & Silicon Bring-Up: Practical knowledge of DFT insertion (Scan, MBIST) and post-silicon laboratory bring-up, testing, and debug. Benefits • Be part of a creative, world-leading team • Competitive salary and share options scheme • Contributory pension scheme • Group private medical insurance scheme • Choose your own laptop/kit • Life Assurance • Cycle-to-work Scheme • Flexible working • Central London location EEO Statement Quantum Motion is committed to providing equal employment opportunity and does not discriminate based on age, sex, sexual orientation, gender identity, race, colour, religion, disability status, marital status, pregnancy, gender reassignment or any other protected characteristics covered by the Equality Act 2010. Internal Job Reference Number HRS-84