Position Summary About Samsung Semiconductor India Research (SSIR) With a wide range of industry-leading semiconductor solutions, we are enabling innovative growth in market segments in component solutions, featuring industry-leading technologies in System LSI, Memory and Foundry. Our engineers are offered a foundation to work on cutting-edge technologies such as Foundation IP Design, Mobile SoCs, Storage Solutions, AI/ML, 5G/ 6G solutions, Neural processors, Serial Interfaces, Multimedia IPs and much more. As one of the largest R&D centres outside Korea for Samsung Electronics, we take pride in our ability to work on some of the cutting edge technologies. Our engineers get to work across diverse domains, projects, products, clients, people and countries, and conduct research in new and emerging technology areas. Innovation and creativity are highly valued at this innovation hub, as we strive towards providing high reliability; high performance and value added services that enable Samsung Electronics deliver world-class products. Role and Responsibilities Roles and Responsibilities This position is for a Senior IP Design Engineer role at Samsung Semiconductor India Bangalore, where you will be involved in RTL design, synthesis and verification of various complex IP modules of Image Sensor products. You will be associated in the design development life cycle to support spec to tape-out defined by specific assignment. You will also be responsible for providing technical inputs or guidance to improve and adhere to hardware development and quality processes necessary to ensure the design consistently meets the required functionality, re-usability, reliability, performance and power targets to ensure Samsung Image Sensors meet their design targets. • Architecture, Design and RTL development for Image Processing IP's. • Technically lead various RTL modules development • Interfacing with cross-functional teams like Algorithm, Verification and Physical Implementation . Ensuring quality of design using Lint and CDC checks. • Synthesis, Area and power optimization.  Necessary Skills / Attributes • Working experience in complex IP Design • Experience in designing and RTL coding using Verilog /System Verilog/VHDL and verifying design with module level test bench or with formal techniques. • Design QC using lint/CDC/DFT • Compile, elaboration and simulations for QC. Experience with Xcellium/VCS, Verdi, and Spyglass. • Understanding of image processing basics, Peripherals, Buses/Interconnects and Power Management. • Experience in writing functional design doc and/or functional specifications. • Experience in synthesis (Synopsys DC, RTL-A) and developing timing constraints (SDC) and Timing analysis. Experience in low power design methodologies and related power estimations, power measurements during implementation. Experience in developing/understanding of ECOs • Working experience in teams with collaboration of effort between Verification, Validation, Physical Design and DFT Additional Qualifications (preferred) • Experience in RTL integration tools like Magillem is added advantage. • Working experience in HLS tools like Stratus/Catapult would be added advantage. Team player, can-do attitude is desirable. Passion for working on innovative technologies, eager to learn and ability to be analyse/debug designs are highly desirable. Skills and Qualifications Experience – 6+ years Qualifications • B.Tech/B.E/M.Tech/M.E Disclaimer Samsung Semiconductor India Research (SSIR), a division of Samsung R&D India - Bangalore Pvt. Ltd is dedicated to employing a diverse workforce and providing Equal Employment Opportunity to all individuals, regardless of their religion, gender, age, marital status, gender identity, status as a protected veteran, genetic information, status as a qualified individual with a disability, or any other characteristic protected by law. * Please visit Samsung membership to see Privacy Policy, which defaults according to your location. You can change Country/Language at the bottom of the page. If you are European Economic Resident, please click here.