Position Summary About Samsung Semiconductor India Research (SSIR) With a wide range of industry-leading semiconductor solutions, we are enabling innovative growth in market segments in component solutions, featuring industry-leading technologies in System LSI, Memory and Foundry. Our engineers are offered a foundation to work on cutting-edge technologies such as Foundation IP Design, Mobile SoCs, Storage Solutions, AI/ML, 5G/ 6G solutions, Neural processors, Serial Interfaces, Multimedia IPs and much more. As one of the largest R&D centers outside Korea for Samsung Electronics, we take pride in our ability to work on some of the cutting edge technologies. Our engineers get to work across diverse domains, projects, products, clients, people and countries, and conduct research in new and emerging technology areas. Innovation and creativity are highly valued at this innovation hub, as we strive towards providing high reliability; high performance and value added services that enable Samsung Electronics deliver world-class products. Roles and Responsibilities Creating the power architecture and specification for the SoC to achieve low power targets and meet all KPIs - Setup environment for the RTL level and gate level power analysis at the pre-silicon stage - Determine tests and benchmarks to run on all IP blocks for pre-silicon power analysis - Identify areas of improvement at the architecture-level, RTL-level, and during synthesis - Determine and set power optimization budgets for IP blocks and execute simulations to validate them during the design stage - Work with industry standard power analysis tools like Power Artist and PrimePower - Document and communicate results with key SoC development and project management personnel Skill Requirements - Good understanding of clock gating, power-gating, DVFS for power optimization - Hands on working experience with power definition, estimation, planning, partitioning, analysis, and optimization - Ability to work in highly competitive consumer SoC designs with strict deadlines and quality standards - Worked on Lower power designs throughout the SoC development cycle from RTL, to gate-level and post-silicon correlation - Good understanding of PMIC, Power electronics, digital electronics concepts - Good to have - Experience with power analysis and power debug tools like PTPX and Power artist - Good programming and scripting skills using Perl, Python/, and TCL - Understanding of CPU, GPU, SoC design - Familiarity with the design flow (synthesis, place & route, power, timing) - Understanding of UPF based low power verification and defining low power strategies Experience – 5 to 14 Years of Experience Qualifications - B.Tech/B.E/M.Tech/M.E Disclaimer Samsung Semiconductor India Research (SSIR), a division of Samsung R&D India - Bangalore Pvt. Ltd is dedicated to employing a diverse workforce and providing Equal Employment Opportunity to all individuals, regardless of their religion, gender, age, marital status, gender identity, status as a protected veteran, genetic information, status as a qualified individual with a disability, or any other characteristic protected by law. Confidentiality Notice: Candidates are reminded that all proprietary information, trade secrets or confidential materials belonging to or obtained from their past or current employers must not be shared or used in connection with their application, interviews, or future employment with our organization Role and Responsibilities Define an efficient IP structure and oversee the task of designing an organically related structure for the IP blocks. Identify the function of the chip and oversee the task of setting objective indicators for special cases or requirement levels when implementing Foundation IP. Skills and Qualifications * Please visit Samsung membership to see Privacy Policy, which defaults according to your location. You can change Country/Language at the bottom of the page. If you are European Economic Resident, please click here.